1. Field
Embodiments relate to a rule-based stacking and wire bonding of semiconductor die in a multi-die semiconductor package.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate in a so-called three-dimensional stacked configuration. An edge view of a conventional semiconductor package 20 (without molding compound) is shown in prior art FIGS. 1 and 2. Typical packages include a plurality of semiconductor die 22, 24 mounted to a substrate 26. While two such die are shown, it is known to stack eight or more die in a semiconductor package. The semiconductor die may be formed with die bond pads, referred to herein as pins, on an upper surface of the die. Substrate 26 may be formed of an electrically insulating core sandwiched between upper and lower conductive layers. The upper and/or lower conductive layers may be etched to form conductance patterns including electrical leads and contact pads. The contact pads are referred to herein as fingers. Wire bonds are soldered between the pins of the semiconductor die 22, 24 and the fingers of the substrate 26 to electrically couple the semiconductor die to the substrate. The electrical leads on the substrate in turn provide an electrical path between the die and a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
As shown in prior art FIG. 1, it is known to stack two or more semiconductor die directly on top of each other, thereby taking up a small footprint on the substrate. However, in a stacked configuration, space must be provided between adjacent semiconductor die for the bond wires 30. In addition to the height of the bond wires 30 themselves, additional space must be left above the bond wires, as contact of the bond wires 30 of one die with the next die above may result in an electrical short. As shown in FIG. 1, it is therefore known to provide a dielectric spacer layer 34 to provide enough room for the wire bond 30 to be bonded to the pin on the lower die 24.
As an alternative to an aligned stack of semiconductor die, it is known to stack semiconductor die on top of each other with an offset as shown in prior art FIGS. 2-4, so that the pins of the next lower die are left exposed. Such configurations are shown for example in U.S. Pat. No. 6,359,340 to Lin, et al., entitled, “Multichip Module Having A Stacked Chip Arrangement.” An offset configuration provides an advantage of convenient access of the pins on each of the semiconductor die. For configurations such as shown in FIG. 2 having a small number of die, for example 2, it is known to wire bond each die in the stack directly to the substrate. However, as indicated above, it is common for die stacks to include 8 or more stacked semiconductor die. In such instances, each die in the stack may be wire bonded to the die directly below, or possibly two below. This configuration is shown in prior art FIGS. 3-4.
In the example shown in FIGS. 3 and 4, the stack includes three semiconductor die 22, 24 and 34, with each being bonded via wires 30 to the die below in the stack. The bottom die 22 may be wire bonded to the substrate 26. Moreover, the corresponding pins on the respective die are wire bonded together. Thus, the pin on die 34 is wire bonded to the first pin on die 24; the first pin on die 24 is in turn wire bonded to the first pin on die 22; and the first pin on die 22 is in turn wire bonded to the first finger on substrate 26. In FIG. 4, this is true for each corresponding pin across the die 34, 24 and 22.
While the above wiring configuration may be possible for data and control pins, wiring of the address pins of die in larger die stacks of greater than four die becomes more problematic. In addition to vertical wire bonds, wire bonds need to be made diagonally, and long jumps between two die that are spaced apart in the stack is required. One reason for this complication is the conventional stacking of die on the substrate in ascending numerical order, as explained in greater detail with respect to prior art FIG. 5. FIG. 5 is a schematic diagram of a typical NAND semiconductor die stack including eight die mounted to a substrate 26. Conventionally the die are stacked one atop another in an offset starting with die 0 and proceeding sequentially to die 7. FIG. 5 also shows the aligned rows of pins from each die, i.e., pins 19 through 23 (other pins not shown). Of these pins, pins 20, 21 and 23 are used chip address pins (CADD2x, CADD1x and CADD0x) to identify each of the die 0-7 in the die stack.
For a given die in the stack, a low voltage to one of pins 20, 21, 23 represents a logical 0 and a high voltage to one of pins 20, 21, 23 represents a logical 1. Thus, using the three address pins on each die, each die in the conventional stack of FIG. 5 may be uniquely addressed sequentially from 000 (die 0) at the bottom of the stack through 111 (die 7) at the top of the stack. FIG. 5 also shows pin 19 which may be the power signal Vcc for each die 0-7, and pin 22, which may be a voltage monitor Vmon. Vmon may often be omitted or left open as shown (with no wire bond connections) in NAND semiconductor packages.
Address pins 20, 21, 23 on the respective die in the stack at a low voltage state may be electrically coupled together via groups of vertical and/or diagonal wire bonds, and then these groups of bonded pins may be bonded to ground contact pads on the substrate. Similarly, address pins 20, 21, 23 on the respective die in the stack at the high voltage state may be electrically coupled together via groups of vertical and/or diagonal wire bonds, and then these groups of bonded pins may be bonded to power contact pads on the substrate. This wire bonding must be accomplished in a way that prevents crossing of wires, which can result in an electrical short.
One drawback to wire bonding of larger die stacks having for example three address pins is that the bonding process is not carried out in a way that minimizes the length of wire required to accomplish all wire bonds. Often, after a first pass of making wire bonds, remaining pins need to be connected to each other that are spaced large distances from each other in the die stack. Such instances require long lengths of wire to make the connection. Wire bonds are typically formed of gold which is expensive. And it is not just the length of wire that is a problem. Longer bond wires are more prone to break, sag or short against adjacent bond wires. Thus, to provide the required rigidity, longer bond wires are made of thicker diameter material. Semiconductor packages are wire bonded using wire from a single spool. Thus, even if there are only a few longer connections that require a thicker diameter wire bond, that same diameter wire is used for all connections. Given the large number of wire bonds in each package, and the large number of fabricated packages, using more and thicker gold wire significantly adds to the cost of package fabrication.
Another problem with conventional wire bonded packages is that more than two ground and power contact pads are required to uniquely address the address pins in the stack. In prior art FIG. 5, a conventional eight die stack having three address pins CADD2x, CADD1x and CADD0x could require a total of six ground (GND) and power (PWR, Vcc) pins to connect the address pins to the substrate. Space on the substrate is at a premium, and it would be advantageous to connect to the address pins using less ground and power pins.